View CAT24C128YE-GT3_3645746.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2009 september, 2009 ? rev. 11 1 publication order number: cat24c128/d cat24c128 128 kb i 2 c cmos serial eeprom description the cat24c128 is a 128 kb serial cmos eeprom, internally organized as 16,384 words of 8 bits each. it features a 64 ? byte page write buffer and supports both the standard (100 khz) as well as fast (400 khz) i 2 c protocol. write operations can be inhibited by taking the wp pin high (this protects the entire memory). features ? supports standard and fast i 2 c protocol ? 1.8 v to 5.5 v supply voltage range ? 64 ? byte page write buffer ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature range ? 8 ? lead pdip, soic, tssop , msop and udfn packages ? this device is pb ? free, halogen free/bfr free and rohs compliant* figure 1. functional symbol sda scl wp cat24c128 v cc v ss a 2 , a 1 , a 0 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com pin configuration sda wp v cc v ss a 2 a 1 a 0 1 see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information soic ? 8 w suffix case 751bd scl pdip (l), soic (w), tssop (y), msop (z), udfn (hu3) pdip ? 8 l suffix case 646aa udfn ? 8 hu3 suffix case 517ax tssop ? 8 y suffix case 948al device address inputs a 0 , a 1 , a 2 serial data input/output sda serial clock input scl write protect input wp power supply v cc ground v ss function pin name pin function for the location of pin 1, please consult the corresponding package drawing. msop ? 8 z suffix case 846ad
cat24c128 http://onsemi.com 2 table 1. absolute maximum ratings parameter rating units storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program / erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c table 3. d.c. operating characteristics (v cc = 1.8 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz 1 ma i ccw write current write, f scl = 400 khz 3 ma i sb standby current all i/o pins at gnd or v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 i l i/o pin leakage pin at gnd or v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 v il input low voltage ? 0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc < 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0 ma 0.2 v table 4. pin impedance characteristics (v cc = 1.8 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter conditions max units c in (note 4) sda i/o pin capacitance v in = 0 v 8 pf c in (note 4) input capacitance (other pins) v in = 0 v 6 pf i wp (note 5) wp input current v in < v ih 200 a v in > v ih 1 a 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 5. when not driven, the wp pin is pulled down to gnd internally. for improved noise immunity, the internal pull ? down is relatively strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull ? down reverts to a weak current source.
cat24c128 http://onsemi.com 3 table 5. a.c. characteristics (v cc = 1.8 v to 5.5 v, t a = ? 40 c to +125 c) (note 6) symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data hold time 0 0 s t su:dat data setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (note 7) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to sda data out 3.5 0.9 s t dh data out hold time 100 100 ns t i (note 7) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (notes 7 and 8) power ? up to ready mode 1 1 ms 6. test conditions according to ?a.c. test conditions? table. 7. tested initially and after a design or process change that affects this parameter. 8. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma (v cc 2.5 v); i ol = 1 ma (v cc < 2.5 v); c l = 100 pf
cat24c128 http://onsemi.com 4 power ? on reset (por) the cat24c128 incorporates power ? on reset (por) circuitry which protects the device against powering up in the wrong state. the cat24c128 will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por feature protects the device against ?brown ? out? failure following a temporary loss of power. pin description scl : the serial clock input pin accepts the serial clock generated by the master. sda : the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address pins accept the device address. when not driven, these pins are pulled low internally. wp : the write protect input pin inhibits all write operations, when pulled high. when not driven, this pin is pulled low internally. functional description the cat24c128 supports the inter ? integrated circuit (i 2 c) bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat24c128 acts as a slave device. master and slave alternate as either transmitter or receiver. up to 8 devices may be connected to the bus as determined by the device address inputs a 0 , a 1 , and a 2 . i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull ? up resistors. master and slave devices connect to the 2 ? wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 2). the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake ? up? call to all receivers. absent a start, a slave will not respond to commands. the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8 ? bit serial slave address. the first 4 bits of the slave address are set to 1010, for normal read/write operations (figure 3). the next 3 bits, a 2 , a 1 and a 0 , select one of 8 possible slave devices and must match the state of the external address pins. the last bit, r/w , specifies whether a read (1) or write (0) operation is to be performed. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 4). the slave will also acknowledge all address bytes and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. as long as the master acknowledges the data, the slave will continue transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by issuing a stop condition. bus timing is illustrated in figure 5.
cat24c128 http://onsemi.com 5 start condition stop condition sda scl figure 2. start/stop conditions 1010 device address figure 3. slave address bits a 2 a 1 a 0 r/w 189 start scl from master bus release delay (transmitter) ack setup ( t su:dat ) bus release delay (receiver) data output from transmitter data output from receiver figure 4. acknowledge timing ack delay ( t aa ) scl sda in sda out figure 5. bus timing t su:sta t hd:sta t hd:dat t f t low t aa t high t low t r t dh t buf t su:dat t su:sto
cat24c128 http://onsemi.com 6 write operations byte write upon receiving a slave address with the r/w bit set to ?0?, the cat24c128 will interpret the next two bytes as address bytes. these bytes are used to initialize the internal address counter; the 2 most significant bits are ?don?t care?, the next 8 point to one of 256 available pages and the last 6 point to a location within a 64 byte page. a byte following the address bytes will be interpreted as data. the data will be loaded into the page write buffer and will eventually be written to memory at the address specified by the 14 active address bits provided earlier. the cat24c128 will acknowledge the slave address, address bytes and data byte. the master then starts the internal write cycle by issuing a stop condition (figure 6). during the internal write cycle (t wr ), the sda output will be tri ? stated and additional read or write requests will be ignored (figure 7). page write by continuing to load data into the page w rite buffer after the 1 st data byte and before issuing the stop condition, up to 64 bytes can be written simultaneously during one internal w rite cycle (figure 8). if more data bytes are loaded than locations available to the end of page, then loading will continue from the beginning of page, i.e. the page address is latched and the address count automatically increments to and then wraps ? around at the page boundary. previously loaded data can thus be overwritten by new data. what is eventually written to memory reflects the latest page write buffer contents. only data loaded within the most recent page write sequence will be written to memory. acknowledge polling the ready/busy status of the cat24c128 can be ascertained by sending read or write requests immediately following the stop condition that initiated the internal write cycle. as long as internal write is in progress, the cat24c128 will not acknowledge the slave address. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no impact on the operation of the cat24c128. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the first data byte (figure 9). if the wp pin is high during the strobe interval, the cat 24c128 will not acknowledge the data byte and the write request will be rejected. delivery state the cat24c128 is shipped erased, i.e., all bytes are ffh. slave address s a c k a c k a c k s t o p p bus activity: master slave s t a r t address byte address byte data byte a c k * = don?t care bit figure 6. byte write sequence ** a 13 ? a 8 a 7 ? a 0 stop condition start condition address ack 8th bit byte n scl sda figure 7. write cycle timing t wr
cat24c128 http://onsemi.com 7 slave address s a c k a c k a c k bus activity: master slave s t a r t address byte address byte data byte n data byte n+1 data byte n+p a c k s t o p a c k a c k p a c k * = don?t care bit p 63 figure 8. page write sequence ** a 13 ? a 8 a 7 ? a 0 1891 8 address byte data byte scl sda wp figure 9. wp timing d 0 d 7 a 7 a 0 t hd:wp t su:wp read operations immediate read upon receiving a slave address with the r/w bit set to ?1?, the cat24c128 will interpret this as a request for data residing at the current byte address in memory. the cat24c128 will acknowledge the slave address, will immediately shift out the data residing at the current address, and will then wait for the master to respond. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 10), the cat24c128 returns to standby mode. selective read to read data residing at a specific location, the internal address counter must first be initialized as described under byte write. if rather than following up the two address bytes with data, the master instead follows up with an immediate read sequence, then the cat24c128 will use the 14 active address bits to ini tialize the internal address counter and will shift out data residing at the corresponding location. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 11), the cat24c128 returns to standby mode. sequential read if during a read session the master acknowledges the 1 st data byte, then the cat24c128 will continue transmitting data residing at subsequent locations until the master responds with a noack, followed by a stop (figure 12). in contrast to page write, during sequential read the address count will automatically increment to and then wrap ? around at end of memory (rather than end of page).
cat24c128 http://onsemi.com 8 scl sda 8th bit stop no ack data out 8 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave figure 10. immediate read sequence and timing 9 slave address s a c k a c k a c k bus activity: master slave s t a r t address byte address byte data byte slave address s a c k p * = don?t care bit figure 11. selective read sequence ** s t a r t s t o p a c k n o a 13 ? a 8 a 7 ? a 0 bus activity: master slave data byte n data byte n+1 data byte n+2 data byte n+x a c k a c k a c k s t o p n o a c k a c k p slave address figure 12. sequential read sequence
cat24c128 http://onsemi.com 9 package dimensions pdip ? 8, 300 mils case 646aa ? 01 issue a e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a a1 a2 b b2 c d e e1 l 0.38 2.92 0.36 6.10 1.14 0.20 9.02 2.54 bsc 3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eb 7.87 10.92 e 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87
cat24c128 http://onsemi.com 10 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat24c128 http://onsemi.com 11 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat24c128 http://onsemi.com 12 package dimensions udfn8, 2x3 case 517ax ? 01 issue o e2 d2 k l e pin #1 index area pin #1 identification dap size 1.3 x 1.8 detail a d a1 b e a top view side view front view detail a bottom view a3 a a1 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.50 1.60 1.70 e 3.00 e2 0.10 0.20 0.30 e 2.90 0.50 typ 3.10 l 0.30 0.35 0.40 k 0.10 ref
cat24c128 http://onsemi.com 13 package dimensions msop 8, 3x3 case 846ad ? 01 issue o e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a a1 a2 b c d e e1 e l 0o 6o l2 0.05 0.75 0.22 0.13 0.40 2.90 4.80 2.90 0.65 bsc 0.25 bsc 1.10 0.15 0.95 0.38 0.23 0.80 3.10 5.00 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.10 0.85
cat24c128 http://onsemi.com 14 example of ordering information prefix device # suffix company id cat 24c128 y product number 24c128 i ? gt3 package i = industrial ( ? 40 c to +85 c) e = extended ( ? 40 c to +125 c) temperature range l: pdip w: soic, jedec y: tssop hu3: udfn (2 x 3 mm) z: msop t: tape & reel 3: 3000/reel lead finish g: nipdau blank: matte ? tin tape & reel (note 9) 9. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. orderable part numbers order number order number cat24c128li ? g cat24c128le ? g cat24c128wi ? gt3 cat24c128we ? gt3 cat24c128yi ? gt3 cat24c128ye ? gt3 cat24c128hu3igt3* cat24c128hu3egt3* cat24c128zi ? gt3 cat24c128ze ? gt3 *part number is not exactly the same as the ?example of ordering information? shown above. for part numbers marked with ?*? there are no hyphens in the orderable part numbers. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat24c128/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of CAT24C128YE-GT3

	To Download CAT24C128YE-GT3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .